Explain when the following sequence matches? What is a sequence repetition operator? What are the three different type of repetition operators used in sequences? If a sequential expression needs to be evaluated for more than one iteration, then instead of writing a long sequence, repetition operator can be used to construct a longer sequence. If a sequence repeats for a finite number of iterations with a delay of one clock tick from end of one iteration, then a consecutive repetition operator can be used. Following is an example of how to use consecutive repetition operator. The overall repetition sequence matches at the last iterative match of the operand. Immediate assertions can be started only inside procedural blocks Write an assertion check to make sure that a signal is high for a minimum of 2 cycles and a maximum of 6 cycles. Following property uses a sequence such that if a signal a rises, then from same cycle, we check it remains high for a minimum of 2 and maximum of 6 cycles and in the next cycle a goes low. What is an implication operator? An implication operator specifies that the checking of a property is performed conditionally on the match of a sequential antecedent. This construct is used to precondition monitoring of a property expression and is allowed only at the property level. The antecedent is the precondition that needs to happen before evaluating the consequent. What is the difference between an overlapping and nonoverlapping implication operator? For overlapped implication, if there is a match for the antecedent sequence_expr, then the endpoint of the match is the start point of the evaluation of the consequent property expression. For non overlapped implication, the start point of the evaluation of the consequent property_expr is the clock tick after the end point of the match of antecedent. No, it can be used only in properties. It is a precondition match to evaluate property expressions. Are following assertions equivalent? These are useful when we have multiple gating conditions leading to a single final consequence. $past is a system task that is capable of getting values of signals from previous clock cycles. Hence this can be used to write an assertion as below. Write an assertion to make sure that the state variable in a state machine is always one hot value. A property can use a disable iff construct to explicitly disable an assertion. Following is an example that disables an assertion check when reset is active high. What’s the difference between assert and assume directives in SystemVerilog? An assert directive is used to specify the property as an obligation for the design that is to be checked to verify that the property holds. An assume directive is same as assert in simulation. It is used to specify the property as an assumption for the environment. Simulators check that the property holds, while formal tools use the assume directive as a constraint information to generate input stimulus. What is bind construct used in SystemVerilog for? This is useful for any instrumentation code or assertions that are encapsulated in a module, interface, program, or checker to be instantiated in a target module or a module instance without modifying the target module code. How can all assertions be turned off during simulation? If no arguments are specified, all the assertions are disabled. If this system task is called in the middle of simulation, then any active assertions at that given point of time are allowed to complete before disabling. What are the different ways in which a clock can be specified to a property used for assertion? In this case property uses that clock. But now they are slowly gaining popularity in Hardware Engineering domain as well. With Hardware Designs becoming more and more complex, various new design features getting integrated every quarter, multiple folks working on the same database across different sites, version control systems have become indispensable. Hence, this section touches upon basics of various Version Control Systems. There are lot of similarities in various commands used in different version control systems. 7.1 General What is a Version Control System? A Version Control System is a database that stores all the change records of your work. What is the need of a Version Control System? When multiple members of a team work together on a shared project, it is important to keep incremental changes of all individual team members in sync in a common database.